1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device, which is fabricated by a four-mask process.
2. Description of Related Art
In general, liquid crystal display (LCD) devices make use of optical anisotropy and polarization properties of liquid crystal molecules to control arrangement orientation. The arrangement direction of the liquid crystal molecules can be controlled by an applied electric field. Accordingly, when an electric field is applied to liquid crystal molecules, the arrangement of the liquid crystal molecules changes. Since refraction of incident light is determined by the arrangement of the liquid crystal molecules, display of image data can be controlled by changing the electric field applied to the liquid crystal molecules.
Of the different types of known LCDs, active matrix LCDs (AM-LCDs), which have thin film transistors and pixel electrodes arranged in a matrix form, are the subject of significant research and development because of their high resolution and superiority in displaying moving images.
LCD devices have wide application in office automation (OA) equipment and video units because of their light, thin, low power consumption characteristics. The typical liquid crystal display (LCD) panel has an upper substrate, a lower substrate and a liquid crystal layer interposed therebetween. The upper substrate, commonly referred to as a color filter substrate, usually includes a common electrode and color filters. Common electrodes function as ground electrodes to prevent liquid crystal cells from breaking down. The lower substrate, commonly referred to as an array substrate, includes switching elements, such as thin film transistors (TFTs), and pixel electrodes.
As previously described, LCD device operation is based on the principle that the alignment direction of the liquid crystal molecules is dependent upon an electric field applied between the common electrode and the pixel electrode. Moreover, because the liquid crystal molecules have a spontaneous polarization characteristic, the liquid crystal layer is considered an optical anisotropy material. As a result of this spontaneous polarization characteristic, the liquid crystal molecules possess dipole moments when a voltage is applied to the liquid crystal layer between the common electrode and pixel electrode. Thus, the alignment direction of the liquid crystal molecules is controlled by the application of an electric field to the liquid crystal layer. When the alignment direction of the liquid crystal molecules is properly adjusted, incident light is refracted along the alignment direction to display image data. The liquid crystal molecules function as an optical modulation element having variable optical characteristics that depend upon polarity of the applied voltage.
The array substrate having the thin film transistors (TFTs) is commonly fabricated by depositing layers and then patterning them using multiple photolithographic processes. When patterning the layers, a five- or six-mask process is generally employed. However, a four-mask process is quite common and widely known for reducing manufacturing costs.
FIG. 1 is a plan view showing a pixel of an array substrate fabricated using a four-mask fabrication process for use in a conventional liquid crystal display device. FIG. 2 is a cross-sectional view taken along line II—II of FIG. 1 and shows a thin film transistor and a storage capacitor.
In FIG. 1, an array substrate 8 includes a region “P” having a corresponding thin film transistor (TFT) “T”, a pixel electrode 81 and a corresponding storage capacitor “S.” Gate lines 21 are arranged in a transverse direction and data lines 61 are arranged in a longitudinal direction such that each pair of gate lines 21 and the data lines 61 define a pixel region “P.” Each TFT “T” includes a gate electrode 22, a source electrode 62, a drain electrode 63 and a channel region “C.” The gate electrode 22 of each TFT “T” extends from the gate line 21, the source electrode 62 of each TFT “T” extends from the data line 61, and the drain electrode 63 is spaced apart from the source electrode 62. Each storage capacitor “S” includes a capacitor electrode 65, a portion of the pixel electrode 81 and a portion of the gate line 21.
In FIGS. 1 and 2, the gate line 21 and the gate electrode 22 are first formed on a substrate 10 by depositing and patterning a first metal layer. A gate insulation layer 30 is formed on the substrate 10 to cover the gate line 21 and the gate electrode 22. On the gate insulation layer 30, first and second intrinsic semiconductor layers 41 and 45, which are pure amorphous silicon, are respectively formed over the gate line 21 and the gate electrode 22. First, second and third extrinsic semiconductor layers 51, 52 and 55, which are doped amorphous silicon, are formed on the first and second intrinsic semiconductor layers 41 and 45. The first intrinsic semiconductor layer 41 disposed over the gate electrode 22 is called an active layer, and the first and second extrinsic semiconductor layers 51 and 52 disposed on the first intrinsic semiconductor layer 41 are called first and second ohmic contact layers, respectively, that enhance contact characteristics between the active layer 41 and the source and drain electrodes 62 and 63. The data line 61, the source electrode 62 and the drain electrode 63 are formed on the first and second extrinsic semiconductor layers 51 and 52 by depositing and patterning a second metal layer. Further, the capacitor electrode 65 is formed on the third extrinsic semiconductor layer 55 and over a portion of the gate line 21 when forming the data line 61 and the source and drain electrodes 62 and 63. Thus, the portion of the gate line 21 functions as the other capacitor electrode of the storage capacitor “S.” A passivation layer 71 is formed on the source and drain electrodes 62 and 63 and the capacitor electrode 65. As shown in FIGS. 1 and 2, the passivation layer 71 is formed along the patterned second metallic material such that the passivation layer 71 covers the data line 61, the source and drain electrodes 62 and 63, and the capacitor electrode 65. Moreover, the passivation layer 71 has the same shape as the patterned second metallic material.
Furthermore, the pixel electrode 81 is formed in the pixel region “P” by depositing and patterning a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO). The pixel electrode 81 contacts side portions of the drain electrode 63 and the capacitor electrode 65. In the storage capacitor “S,” the pixel electrode 81 overlaps not only a portion of the capacitor electrode 65 but also a portion of the gate electrode 21.
FIGS. 3A to 3C are cross-sectional views taken along line II—II of FIG. 1 and show conventional fabricating processes of an array substrate using a four-mask process.
Referring to FIG. 3A, a first metal layer is deposited on the substrate 10 and patterned using a first mask to form the gate line 21 along a transverse direction and a gate electrode 22 that extends from the gate line 21. A material for forming the first metal layer includes chromium (Cr), molybdenum (Mo), and aluminum (Al) or alloys thereof.
Now, referring to FIG. 3B, a gate insulation layer 30, a pure amorphous silicon layer 40 and a doped amorphous silicon layer 50 are sequentially formed on the substrate 10 to cover the patterned metal layer. Thereafter, the second metal layer 60 is deposited on the doped amorphous silicon layer 50 using a sputtering method. Then, the second metal layer 60 is patterned to form a channel region “C” over the gate electrode 22. Namely, portions of both the second metal layer 60 and the doped amorphous silicon layer 50 over the gate electrode 22 are etched using a second mask to form the channel region “C” in the pure amorphous silicon layer 40.
Referring to FIG. 3C, an inorganic material, such as silicon nitride (SiNx) or silicon oxide (SiOx), is deposited on the patterned second metal layer 60 (in FIG. 3B). Thereafter, the inorganic material, the second metallic material 60, the doped amorphous silicon layer 50 and the pure amorphous silicon layer 40 are simultaneously patterned using a third mask, thereby forming the passivation layer 71, the data line 61, the source electrode 62, the drain electrode 63, the capacitor electrode 65, the first, second and third extrinsic semiconductor layers 51, 52 and 55, and the first and second intrinsic semiconductor layers 41 and 45.
Thereafter, referring back to FIG. 2, a transparent conductive material is deposited over an entire surface of the substrate 10 and patterned using a fourth mask. Therefore, as described above, the pixel electrode 81 is formed in the pixel region “P” (in FIG. 1). Further, one portion of the pixel electrode 81 contacts the side portion of the drain electrode 63 and overlaps a portion of the drain electrode 63, while another portion of the pixel electrode 81 contacts a side portion of the capacitor electrode 65 and overlaps a portion of the capacitor electrode 65.
As previously described, since the array substrate is fabricated by the four-mask process, the manufacturing costs decrease. However, some significant problems occur as a result of the aforementioned fabrication process.
FIG. 4A is an enlarged view of a portion “A” of FIG. 1, and FIG. 4B is an enlarged cross-sectional view taken along line IV—IV of FIG. 4A.
As described before, the inorganic material, the second metal layer, the doped amorphous silicon layer and the pure amorphous silicon layer are simultaneously etched during the third mask process. Therefore, only the gate insulation layer 30 remains in the pixel region “P”. Further, as shown in FIG. 4B, a portion “B” of the gate insulation layer 30 located on the step portion of the gate line 21 may be removed after the third mask process. While patterning the transparent conductive material during the fourth mask process, the portion “B” of the gate insulation layer 30 may suffer insulator breakdown. During insulator breakdown, the gate line 21 and the date line 61 are electrically short-circuited at the crossover point of the gate line 21 and the data line 61. As a result, manufacturing defects can occur in the array substrate, thereby decreasing manufacturing yields of the LCD device.